Synchronous clocking systems are set up such that data flows from one group of state devices to the next, synchronized with the clock. In computer systems, generally, the synchronous clocking is either single phase or multi-phase. The type of clock system chosen for a computer design is based upon the type of state device chosen in the design along with other timing constraints.
The two most common types of state devices used in typical high speed computers include the so-called "flip flop and latch" or "master-slave flip flop." A flip flop is an electronic state device capable of exhibiting either of two stable states and of switching between these states in a reproducible manner. In a logic circuit, the two states are made to correspond to logic 1 and logic 0. Flip flops are therefore one-bit memory elements which are used in digital processors.
Flip flops are available in various forms including "D flip flops" and "master-slave flip flops". A D flip flop is a clocked flip flop having a single input D. The D flip flop output Q takes on the current state of the D input only when a given transition of the clock signal occurs between its two logic states. A master-slave flip flop includes master and slave elements that are clocked on complementary transitions of the clock signal. Data is only transferred from the master element to the slave element, and hence to the output, after the master device outputs have stabilized. Master-slave operation eliminates the possibilities of ambiguous outputs, which can occur in single element flip flops as a result of propogation delays in driving the flip flops.
A latch is a state device that can be considered as an extension of a flip flop, which temporarily stores a single bit of data. The storage is controlled by a clock signal, a given transition of which fixes the latch output at the current value of its input. During the period in which the clock signal is open, data supplied to the input of the latch flows through to the latch output (flow through latch). Generally, master-slave flip flops contain two latches i.e., a master and a slave. These state devices can be described with respect to their various parameters which are defined below and used throughout the specification:
"C" is the cycle time or period for the clock cycle.
"T.sub.pd " is the propagation delay time through the state device and is defined as the time interval between a change on the device's clock or data input until the corresponding change on the output.
"T.sub.su " is the "data to clock set up" time for a state device and is defined as the minimum time interval during which the device data input must be held stable before the arrival of the latching edge of the clock pulse.
"T.sub.hld " is the clock to "data hold time" for a state device and is defined as the minimum time interval during which the device data input must be held stable after the latching edge of the clock pulse has been removed.
"S" is the clock skew defined as the undesired difference between arrival times of the clock signals at any pair of destinations, where the arrival times are expected to be substantially identical.
"W" is the width of the clock pulse, corresponding to the time period in which a latch is held open.
"MIN" or "MINPATH" is the minimum amount of delay necessary to insure a race-free transfer of data between two state devices.
"MAX" or "MAXPATH" is the maximum amount of delay that is allowed between two state devices.
Prior computers have extensively used master-slave flip flops in their VLSI designs. To operate properly on a VLSI chip, however, master-slave flip flops typically require twice as much power and twice as much area as a simple latch.
The use of only one simple latch in place of a master-slave flip flop or state device in a VLSI design has been very difficult to implement due to the timing constraints imposed by the necessary clocking required. There is therefore a need for a simple latch design which functions as a master-slave flip flop replacement while operating properly in conjunction with the synchronous clock system of a high speed computer.